The present disclosure relates to a semiconductor integrated circuit including flip-flop memory cells, and more particularly to a test function for extracting a defective memory cell.
The degree of integration of semiconductor integrated circuits has been increased over the years. As a circuit which is particularly required to be formed with a high degree of integration since the data processing amount has been increased, static random access memory (SRAM) which stores data is known. In a SRAM, flip-flop memory cells are integrated on a large scale. Despite its high degree of integration, stored data has to be held at all the time, all of memory transistors have to correctly operate at the same time.
However, as the degree of integration increases due to reduction in process size, defects in some transistors forming SRAM memory cells might be caused during process steps, and thus, defective memory cells which cannot hold data correctly might be generated.
A memory cell in which a defect has been caused has to be detected by a test and replaced with a redundant memory cell which operates correctly before shipping. However, for some defective memory cells, many steps are required for detecting defects. For example, there are defective memory cells which pass a test at room temperature which is normally performed, but cannot hold data and fail a test at low temperature.
As one of examples of such defective memory cells, there is a defective memory cell in which process to a contact of a PMOS transistor forming a flip-flop with a power supply source is not sufficient, and thus a resistance is increased as compared to a normal memory cell. In such a defective memory cell, a current power supply from the power supply source is not sufficient, and thus, a state in which high data is held becomes unstable.
Conventionally, test circuits which extract such defective memory cells have been proposed (for example, see the specification (FIG. 3) of U.S. Pat. No. 6,778,450). FIG. 5 illustrates the configuration of such a test circuit. In the configuration of FIG. 5, separately from a write circuit used during a normal operation, a write test circuit 108 is provided to a memory cell 112. At a test, when the bit line BL side is tested, a test write signal WW0 rises, and when the bit line XBL side is tested, a test write signal WW1 rises. For example, when the test write signals WW0 and WW1 become a low level and a high level, respectively, NMOS transistors QN11 and QN14 become conductive, and NMOS transistors QN12 and QN13 are maintained nonconductive. As a result, a potential of (Vdd−Vtn) is supplied to a bit line BL via a PMOS transistor QP8 and the NMOS transistor QN11. On the other hand, a weak write potential Vww is supplied to a bit line XBL via NMOS transistors QN15 and QN14.
The weak write potential Vww is an intermediate potential between the Vss level and the Vdd level, and is adjusted by a bias potential WBIAS to be supplied to a gate of the NMOS transistor QN15. The weak write potential Vww is set to a potential with which data write to a high data holding node of a normal memory cell cannot be performed but data write to a high data holding node of a defective memory cell can be performed. That is, when a resistance of a source of a PMOS transistor in a memory cell has been increased, a stored data is inverted by supplying the intermediate potential which is low enough not to cause inversion of stored data in a normal memory cell via a bit line. Thereafter, data is read and whether the inversion took place or not is verified, thereby identifying a defective memory cell.